This value is compared with the current values flowing in each branch, read by the ADC. Since we have two branches in our converter, the total current is divided by two. The output of this PID processing is the reference current. The error voltage generated by comparing the real output voltage and the reference voltage (the voltage we want to get at the output) is processed by the voltage PID. One (complimentary, if synchronous buck) PWM channel for Buck 2.One (complimentary, if synchronous buck) PWM channel for Buck 1.One ADC channel for the second inductor current measurement.One ADC channel for the first inductor current measurement.Apart from the power circuits, everything is inside the dsPIC. We can see that the current ripple is at double the frequency of the PWM signal (higher frequency ripple is easier to filter out because a smaller L and C are required) and the ripple amplitude is smaller compared to every single ripple.Ī multi-phase converter in average current mode can also be implemented using a dsPIC. They are 180° of out-of-phase.Īs a result, the total output current is the sum of the two inductor currents. The diagram below shows the two waveforms that represent the currents into the two inductors. The two PWM signals are then generated with a 180° phase shift. Traditional buck architecture is doubled and the two outputs are connected together.The designer wants to reduce the current ripple.Multi-Phase architectures are mainly used when: The current error is processed by the second PID controller and the output value is the duty cycle value. The output of this PID processing is the reference current and it is compared with the current value that is read by the ADC. The error is generated by comparing the real output voltage and the reference voltage. One (complimentary, if synchronous buck) PWM channel.One ADC channel for the inductor current measurement.One ADC channel for the output voltage measurement.

The following shows how a buck converter in average current mode can be implemented using dsPIC®. The compensators are normally designed using op-amp and passive components. Note that controlling the peak of the current has the same effect as controlling the average current.Ī final note: In an analog implementation, the SAW generator, the comparator (or the summing node) and the flip–flop (including associated control circuitry) are generally embedded in a single chip, typically referred to as the PWM generator. This is true when, in each PWM period, the inductor current does not go to zero. PCM control, under certain conditions, is equivalent to ACM control. The ACM directly controls the average current. At this point, the importance of ACM control should be clear.

This means that the output current will be the inductor average current. In an ideal condition, the ripple current will completely and exclusively flow to ground through the cap. The output cap is seen as a short circuit to the ground by the ripple component of the current. Therefore, the inductor current has two contributions: However, the inductor current has a quite wide ripple, due to the ramp up and ramp down of the current itself.

In the specific case of the buck converter (note that similar reasoning holds for other topologies) the current flowing into the inductor is also the current flowing to the output. The comparator output drives through the two usual flip-flops that control the switches.Ī simplified explanation of the differences between average and peak current mode loops is provided below. The current error is then processed by the current compensator (pink box) to generate a signal that is compared with the locally generated sawtooth signal. Inner loop: This loop measures the average current flowing into the inductor and compares it to the reference current.Outer loop: This is the voltage control loop where the comparison of the output voltage with the reference voltage provides the error this is processed by the voltage compensator (green box).Average current mode loop is quite similar to peak current mode architecture in that there are two loops: The diagram below presents the third possible control loop system - Average Current Mode (ACM) and explains how it may be operated in an analog implementation.

Dspic filter designer